TITLE

Building Energy-Efficient, High-Performance Circuits and Architectures Tailored to Machine Learning Computation

PRESENTER

Prof. Ian O'Connor, École Centrale de Lyon, France

DESCRIPTION

This talk explores how next-generation circuits and architectures can be co-designed to meet the stringent energy-efficiency and performance demands of modern machine learning workloads. It highlights a cross-layer approach that spans emerging device technologies - such as ferroelectric FETs, reconfigurable transistors, and silicon photonics - to novel computing paradigms including in-memory, approximate, and stochastic computing. By leveraging device-specific properties and integrating them into architecture-level innovations, we demonstrate how data movement can be minimized, parallelism enhanced, and energy consumption drastically reduced. The presentation also emphasizes design-technology co-optimization (DTCO) methodologies, enabling a tight coupling between materials, devices, circuits, and system architectures. Through selected case studies, the talk illustrates how these synergistic strategies pave the way for scalable, high-performance, and energy-efficient hardware tailored to the unique characteristics of machine learning computation.

ABOUT THE SPEAKER

Ian O'Connor is Professor for Heterogeneous and Nanoelectronics Systems Design in the Department of Electronic, Electrical and Control Engineering at Ecole Centrale de Lyon, France. He is joint head of the Electronics group at the Lyon Institute of Nanotechnology, and Director of the SoC2 research network. Since 2008, he also holds a position of Adjunct Professor at Ecole Polytechnique de Montréal, Canada. His research interests include novel computing architectures based on emerging technologies, associated with methods for design exploration. He has authored or co-authored close to 300 book chapters, journal publications, conference papers and patents, has held various positions of responsibility in the organization of many international conferences and has been workpackage leader or scientific coordinator for several national and European projects. He also serves as an expert with Collège Numérique France 2030, International Roadmap for Devices and Systems (IRDS) Systems and Architectures International Focus Team, International Federation for Information Processing (IFIP) WG10.5 (Design and Engineering of Electronic Systems), is Vice-President for Technical Activities in the IEEE Council for Electronic Design Automation (CEDA), is a member of the Main Board of the European Design Automation Association (EDAA) and is Associate Editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.